This invention relates to phase-locked loop circuits for programmable logic devices. More particularly, this invention relates to an apparatus and method for decreasing the lock time of a phase-locked loop over a wide range of frequencies.
Programmable logic devices include phase-locked loop (“PLL”) or delayed-lock loop (“DLL”) circuitry to counteract “skew” and excessive delay in clock signals propagating on the device. See for example, Jefferson U.S. Pat. No. 5,699,020 and Reddy et al. U.S. Pat. No. 5,847,617, both of which are incorporated herein by reference.
PLL circuits include circuitry to generate an oscillating signal that is phase/frequency locked with a reference clock. The oscillating signal is controlled and maintained in response to a control voltage, which is generated and maintained by the circuitry of the PLL. When a PLL is powered up, the control voltage is set to a predetermined value. The PLL then adjusts the control voltage up or down depending on the desired output frequency of the PLL. After reaching the desired output frequency, the PLL further continues to make fine adjustments to the control voltage until the output signal is in phase with the reference signal. Once the control voltage reaches a value where the desired output phase/frequency is achieved, the PLL is locked. And thereafter the PLL circuitry maintains that control voltage.
Normal operations on an electronic device such as a programmable logic device, are generally not available until the PLL is locked with the reference signal. Thus, it is desirable to reduce the amount of time required for the PLL to lock.
Existing methods reduce the lock time of a PLL circuit by setting the starting voltage of the PLL to ½ Vcc. Where a user setting requires the control voltage to be something other than ½ Vcc, the PLL starts at ½ Vcc and then the PLL circuitry adjusts the control voltage up or down until the control voltage reaches the desired value. Again, normal operations on the electronic device are not available while the PLL circuitry makes this adjustment.
Although the above technique reduces the PLL lock time, it is unsatisfactory where the PLL must operate over a wide range of frequencies. Consequently, there is a need in the art for a method and apparatus to reduce the lock time of a PLL where the PLL must operate over a wide range of frequencies.